1. Field of the Invention
This invention relates to a semiconductor device that has a thin film transistor formed on a substrate and a storage capacitor formed adjacent to the thin film transistor for holding voltage supplied through the thin film transistor. This invention also relates to a manufacturing method of the semiconductor device.
2. Description of the Related Art
FIG. 4 is a diagram of a conventional liquid crystal display device. A liquid crystal panel 150 has a plurality of pixels formed in a matrix configuration with n-rows and m-columns. Each of the pixels has a pixel selection thin film transistor (referred to as the TFT, hereinafter) 10, a liquid crystal LC, and a storage capacitor Csc.
A gate line 20 extending in a row direction is connected to the gate of the TFT 10, and a data line 22 extending in a column direction is connected to the drain of the TFT 10. A gate scanning signal is sequentially supplied from a vertical driving circuit 130 to the gate line 20 of each row and the TFT 10 is selected accordingly. Also, a video signal is applied to the liquid crystal LC through the TFT 10 based on a drain scanning signal supplied from a horizontal driving circuit 140. The storage capacitor Csc is used for holding the video signal supplied through the TFT 10.
FIG. 5 is a plan view of the pixel described above. FIG. 6 is a cross-sectional view of the pixel along with the Y—Y line in FIG. 5. Also, FIG. 5 is a plan view looking from the backside of a first substrate 100. The liquid crystal display device has the first substrate 100 made of a transparent insulating material such as glass, a second substrate 500, and a liquid crystal 200 inserted between the two substrates.
A semiconductor layer 14 (for example, a poly-silicon layer) of the TFT 10 is bent and intersects the gate line 20 straightly extending in a row direction at two points in the pixel. A channel region 14c is formed at each location where the semiconductor layer and the gate line cross each other. The gate line 20 has a double gate configuration.
A gate insulating layer 66 is formed between a gate electrode which is a part of the gate line 20 and the channel region 14c. A drain region 14d of the semiconductor layer 14 is connected to the data line 22 extending in a column direction through a contact hole C0 formed in an interlayer insulating film 68 and the gate insulating layer 66.
A source region 14s of the semiconductor layer 14 is connected to a metal wiring 40 through a contact hole C1 formed in the interlayer insulating film 68 and the gate insulating layer 66. The metal wiring 40 is formed in the same layer (for example, an aluminum layer) as the data line 22 and disposed on the interlayer insulating film 68. The metal wiring 40 is also connected to a pixel electrode 24 located in an upper layer through a planarization insulating film 72 disposed above the metal wiring 40.
Also, the storage capacitor line 42 is formed in the same layer (for example, molybdenum film, chrome film) as that of the gate line 20. The storage capacitor line 42 extends straightly in the row direction and is formed above a part of the semiconductor layer 14 with the gate insulating layer 66 between the storage capacitor line 42 and the semiconductor layer 14. The area where both the capacitor line 42 and the semiconductor layer 14 are configured to operate as a storage capacitor Csc.
Japanese Patent Application Publication No. Hei 1-129234 discloses the liquid crystal display device described above.
However, the gate insulating layer 66 located beneath the gate electrode of the TFT 10 sometimes suffers from the dielectric break down or the leakage during the manufacturing process. The cause of this kind of trouble will be explained below.
FIG. 7 shows the cross-sectional view of the manufacturing process of the liquid crystal display device and corresponds to the cross-section along with the Y—Y line in FIG. 5. A dry etching method is employed for processing the gate line 20 and the storage capacitor line 42. Static charge is stored in the gate line 20 and the storage capacitor line 42 during this process. When the ion implantation of an N-type impurity, such as arsenic or phosphorus, into the semiconductor layer 14 is performed for forming the source region 14s and the drain region 14d using the gate line 20 as a mask, static charge is also stored in the gate line 20 and the storage capacitor line 42 due to charging-up phenomena. The gate line 20 and the storage capacitor line 42 tend to store static charge easily because they extend across the liquid crystal panel 100.
Therefore, the voltage induced at the gate line 20 and the storage capacitor line 42 increases, having the voltage of the semiconductor layer 14, which makes a capacitance coupling with the two lines, increase. With this condition, the storage capacitor line 42, for example, discharges stored charges. This electric discharge tends to occur between the storage capacitor line 42 and the pattern of the vertical driving circuit 130 that is located near the storage capacitor line 42. Then, the voltage of the storage capacitor line 42 drastically decreases, having the voltage of the semiconductor layer 14, which makes a capacitance coupling with the line, also drastically decrease. Therefore, there will be a big discrepancy in voltage in the gate insulating layer 66 between the gate line 20 and the semiconductor layer 14, causing the dielectric breakdown or the leakage at the location A shown in FIG. 7. This type of trouble causes a line defect and point defect when the completed liquid crystal display device forms a display image.